Semiconductor integrated circuit device

ABSTRACT

A semiconductor integrated circuit device utilizing a memory cell containing a transistor to write information and a storage MOSFET to retain an information voltage in the gate, a word line placed to intersect with a write data line and a read data line, for connecting to the control terminal of the write transistor and a memory cell array for issuing an output on the read data line corresponding to the read signal from said memory cell in response to a select signal from said write transistor and by means of a data select circuit select one from among said plurality of read data lines from the data line select circuit and connect to either a first or second common data line, precharge said read data line to a first voltage within a first period, discharge said read data line to a second voltage by means of a second storage MOSFET of said memory cell set to on status for said word line selected within the second period, precharge said first and second common data lines to a third voltage between said first and said second voltages within said first period and, amplify the read signal appearing on either of the common data lines from the read data line selected by said data line select circuit within said second period by using the precharge voltage on said other common data line as a reference voltage.

FIELD OF THE INVENTION

This invention relates to a semiconductor integrated circuit device andrelates in particular to a high reliability, large capacitysemiconductor memory circuit.

BACKGROUND OF THE INVENTION

Semiconductor memories are broadly classified into RAM (random accessmemories) and ROM (read only memory) devices. Among these devices, thedynamic RAM (DRAM) is used in the largest numbers as the main memory forcomputers. The memory cells that store the information are composed ofone capacitor and a transistor to read out the charge stored on thatcapacitor. This memory cell can form the smallest structural element onthe RAM and is therefore ideal for use on a large scale. Accordingly,this large scale use results in making these memory cell devices idealfor mass production at a low price.

However, the DRAM has a problem in that operation tends to be unstable.The largest cause of this instability is that the memory cell itself hasno amplifying effect and therefore the read out signal voltage from thememory cell is small and the memory cell operation is susceptible to allkinds of random noise. Another drawback is that the information chargestored in the capacitor is lost due to the leakage current in the pnjunction within the memory cell. Before this charge is lost, a refresh(rewrite) operation is performed periodically on the memory cell toretain the memory information stored in the memory cell. The period isreferred to as the refresh period and currently requires approximately100 milliseconds, however this refresh period becomes longer as thememory capacity increases. In other words, the leakage current must belimited but restricting the leakage current becomes more and moredifficult as the elements become smaller.

A memory to solve these problems was the ROM and the flash memory inparticular. As is well known, the flash memory is at least as small as aDRAM cell and the memory cell has internal gain so that the signalvoltage is essentially large, and operation is therefore stable. Astorage charge is also accumulated in the storage node enclosed by aninsulator film so that like the DRAM, there is no current leakage fromthe pn junction and a refresh operation is not required. However, a weaktunnel current flows to accumulate the charge in the storage mode sothat the write time is extremely long. Also, repeating the writeoperation causes electrical current to flow in the insulator film andthe insulator film gradually deteriorate and finally the insulator filmbecomes a conductive film that is unable to retain information.

The ROM device is therefore generally limited to about 100,000 writeoperations. In other words, the flash memory cannot be utilized as aRAM. The DRAM and flash memory therefore both have a large capacitymemory and respective advantages and disadvantages. The particularadvantages of each device have to be considered when using the device.

A method of the known art for a three transistor cell comprised of astorage MOSFET to store an information voltage in a gate, and a writeMOSFET to write an information voltage in a gate was disclosed forinstance in “Ultra LSI Memories” Baifukan, Nov. 5, 1994 Kiyoo Itoh, PP.12-15. The three-transistor cell of this type had an amplificationfunction in the cell itself so that the signal voltage appearing in thedata line was large, and read out was totally non-destructive howeverthis device also had problems since the peripheral circuits for read andwrite operations were complicated and difficult to use so that the threetransistor cell was not practical to use.

In view of the above problems with the prior art, it is an object of thepresent invention to provide a semiconductor integrated circuit devicehaving a memory circuit with simple circuit structure that is also easyto use.

Yet another object of the present invention is to provide asemiconductor integrated circuit device having a memory circuit that isboth high speed and nonvolatile. The above mentioned and other newfeatures and objects of this invention will be apparent to one skilledin the art from the description of this invention and the accompanyingreference drawings.

SUMMARY OF THE INVENTION

A simple description of the concept of the invention as disclosed inthis application is as follows. A semiconductor device has a memory cellarray comprised of memory cells containing a write transistor and astorage MOSFET for holding an information voltage in the gate, a wordline intersecting with a write data line for conveying write informationvoltages and an intersecting read line for conveying read informationsignals corresponding to the on or off state of the storage MOSFETmemory cell, the control terminals of the write transistors of thememory cell are connected by the word lines and the read signal isoutput on the corresponding read data line in response to the selectsignal from the write transistor control terminals, and one read dataline is selected from among a plurality of read data lines by the dataline select circuit and is connected to either a first or second commondata line, the selected read data line is precharged to a first voltagepotential in the non-select period, in a first select period that wordline is selected for read out and discharged to a second voltagepotential by the on status of the storage MOSFET of the memory cell, thefirst and second common data lines are precharged to a third voltagepotential between the first and second voltage potentials in thenon-select period, the read signal appearing in the first select periodon the read data line selected by the data line select circuit and inone common data line corresponding to the dispersed charge are amplifiedusing the precharge voltage of another common data line as the referencevoltage, after the write signal is conveyed on the write data line, whennecessary, in the second select period the word lines are set to a highvoltage and the write transistor is set to on status to perform write orrewrite in the memory cell.

A simple description of another representative concept of the inventionas disclosed in this application is as follows. Namely, a semiconductordevice has a memory cell array comprised of memory cells containing awrite transistor and a storage MOSFET for holding an information voltagein the gate, a word line intersecting with a write data line conveyingwrite information signals and an intersecting read data line conveyingread information signals corresponding to the on or off state of thestorage MOSFET of the memory cell, the control terminals of the writetransistors of the memory cell are connected by the word lines, and theread signal is output on the corresponding read data line in response tothe select signal from the control terminals, a sense amplifiercomprised of a CMOS latch structure is formed between the write dataline and the read data line, that read data line is precharged to afirst voltage potential in a first period, that write data line isprecharged to a second voltage smaller than the first voltage in thefirst period, the word line is selected in a second period and the readdata line is discharged to a third voltage potential by the on status ofthe storage MOSFET of the memory cell, the sense amplifier is set tooperating status after the read data line has been set to the firstvoltage or the third voltage corresponding to the memory cellinformation voltage and the high level or low level state is amplifiedaccording to the operating voltage of the sense amplifier, and a dataline select circuit selects one pair of data lines from among aplurality of pairs comprised of read data lines and their correspondingwrite data lines and connect that data line pairs to a first and secondcommon data line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an essential portion of a circuit schematic showing anembodiment of the memory circuit comprising the semiconductor integratedcircuit of this invention.

FIG. 2 is an essential portion of a circuit schematic showing anotherembodiment of the memory circuit comprising the semiconductor integratedcircuit of this invention.

FIG. 3 is a concept view of the cross sectional structure for anembodiment of the BMOS transistor utilized in the circuit of FIG. 2.

FIG. 4 is a graph of the voltage/current characteristics of the BMOStransistor shown in FIG. 3.

FIG. 5 is a concept plan view of an embodiment of the memory cell forthe circuit of FIG. 2.

FIG. 6 is a cross sectional view of the memory cell of FIG. 5 takenalong lines A-A′.

FIG. 7 is a cross sectional view of the memory cell of FIG. 5 takenalong lines B-B′.

FIG. 8 is a waveform chart for describing one example of the memorycircuit operation of FIG. 1 and FIG. 2.

FIG. 9 is an essential portion of a circuit schematic showing anotherembodiment of the memory cell comprising the semiconductor integratedcircuit of this invention.

FIG. 10 is an essential portion of a circuit schematic showing anembodiment of the memory cell comprising the semiconductor integratedcircuit of this invention.

FIG. 11 is a waveform chart for describing one example of the memorycircuit operation of FIG. 10.

FIG. 12 is an essential portion of a circuit schematic showing anembodiment of the memory cell comprising the semiconductor integratedcircuit of this invention.

FIG. 13 is a waveform chart for describing one example of the memorycircuit operation shown in FIG. 12.

FIG. 14 is an essential portion of a circuit schematic showing anembodiment of the memory cell comprising the semiconductor integratedcircuit of this invention.

FIG. 15 is an essential portion of a circuit schematic showing yetanother embodiment of the memory cell comprising the semiconductorintegrated circuit of this invention.

FIG. 16 is a waveform chart for describing one example of the memorycircuit operation shown in FIG. 15.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereafter, a detailed description of this invention will be given whilereferring to the related drawings.

FIG. 1 is a circuit schematic showing an example of the memory circuitcomprising the semiconductor integrated circuit of this invention. Eachof the element and circuit blocks are formed by semiconductor integratedcircuit manufacturing technology of the known art on a semiconductor(LSI) substrate made of single crystalline silicon.

In this embodiment, the data lines are separated into a read data linesRD and write data lines WD with no particular restrictions, howeverthese lines extend in parallel in a perpendicular direction. In FIG. 1,the read data lines RD and write data lines WD are provided in pairsfrom 1 to n number of pairs and of these data line pairs, two pairsconsisting of data line pair RD1, WD1-RDm and WDm are used as examples.

In one memory array MA1, one or n pairs of word lines WL11-WL1n extendin the horizontal direction so as to cross the plurality of data linepairs RD1, WD1-RDm and WDm. Of these plurality of word lines 1 throughn, two pairs of word lines WL11 and WL1n are used as examples. Theseword lines are not subject to any particular restrictions but aplurality of memory arrays MA1-MAk from 1 through k are formed in thedirection of the data lines and in each memory array MA, a plurality ofword lines 1 through n, are formed the same as each memory array MA1.

The structure of the memory array is next explained using the memoryarray MA1 as an example. A memory cell MC11 formed at the cross point ofthe word line WL11 and the data lines RD1, WD1, is comprised of astorage MOSFET QR to retain an information voltage at its gate and setto on or off status when the word line WL11 is selected according tothis information voltage, a write MOSFET QW at the gate of the MOSFET QRfor conveying the write signal of the write data line WD, and acapacitor C formed between the gate of the MOSFET QR and the word lineWL11 to set the MOSFET QR to off status regardless of the memory voltagewhen the word line is not selected.

The gate of the write MOSFET QW is connected to the word line WL11. Thesource/drain path of the storage MOSFET QR is connected to the read dataline RD1 and the ground voltage VSS (o volts) of the circuit.

A precharge MOSFET QPR and QPW with switching being controlled by theprecharge signal PR, are formed on the read data line RD1 and the writedata line WD1, and the data lines RD1 and WD1 are precharged to voltageVDD in the precharge period.

A write control circuit WC1 is formed between the read data line RD1 andthe write data line WD1 to convey the read data line RD1 signal to thewrite data line WD1. There are no particular restrictions in thisembodiment and the write control circuit WC1 is comprised of a MOSFETQT1 whose switching is controlled by a control line WCL1 extending inparallel with the word line WL.

The data lines RD2, WD2 formed the same as the adjoining pair of datalines RD1 and WD1, also have an identical memory cell, precharge circuitand write control circuit.

The read data lines RD1 through RDm are connected to either of a pair ofcomplementary common data lines /IO(1) and IO(1) by way of switch MOSFETQY11 through QY1m comprising the data line select circuits. There are noparticular restrictions but the read data lines RD1 through RDm formedin the memory array MA1 are configured of even-numbered lines, and forinstance the odd-numbered read data lines RD1, RD3, . . . are connectedto the common data lines IO (1) and the even-numbered read data linesRD2, RD4, . . . RDm are connected to the common data lines /IO(1).

The number of read data lines connected to the pair of the complementarycommon data lines IO(1) and /IO(1) are therefore equal and the number ofswitch MOSFETs comprising the data line select circuit corresponding tothe common data lines IO(1) and /IO(1) are also equal. The common datalines IO(1) and /IO(1) have an equivalent length and are also connectedto the same number of switch MOSFETs and so have largely the sameparasitic capacitance.

Here, the complementary common data lines are comprised of an invertedcommon data line /IO in which a low level corresponds to a logic 1, anda non-inverted complementary common data line IO (1) in which a highlevel corresponds to a logic level 1, the slash / indicates the overbarof the logic symbol.

A MOSFET Q1 and MOSFET Q2 are formed in the complementary common datalines IO(1) and /IO(1) to precharge to a half-precharge voltage VDD/2corresponding to one-half of the discharge voltage (0 volts) andprecharge voltage (VDD) of the read data line. The gates of the MOSFETQ1 and Q2 are supplied by the precharge signal PR. Identical common datalines and precharge circuits are also formed in the other memory arraysMA2 through MAk.

The plurality of word lines WL11 through WL1n, and WLKk1 through WLKnformed in the memory arrays MA1-MAk are selected one line apiece by theX decoder & drivers X-DEC/DRV for the memory arrays MA1-MAk.

The select signals YS1 through YSm formed by means of the Y decoder &driver Y-DEC/DRV simultaneously select the read data lines RD1-RDk thatcorrespond to the memory arrays MA1-MAk, and connect the read data linesRD1-RDk to any or any one of the corresponding common data lines IO(1),/IO(1) through IO(k), /IO(k). Consequently, memory access is performedin k bit units consisting of 1 through k in this embodiment of thememory circuit. A simplified circuit can therefore be achieved byutilizing the Y decoder & driver Y-DEC/DRV such as mentioned above, incommon with the data line selection operation for the memory arrays MA1through MAk.

There are no particular restrictions on the common data lines IO (1) and/IO(1) and a CMOS latch circuit formed as the sense amplifier SA1consists of an N-channel MOSFET QN1 and QN2 as well as P-channel MOSFETQP1 and QP2 that form CMOS inverter circuits with intersecting input andoutput connections. The sense amplifier SA1 consisting of these CMOSlatch circuits is configured so that the respective common sources SNand SP for the N-channel MOSFET QN1, QN2 and the P-channel MOSFET QP1and QP2 are enabled by application of operating voltages such as supplyvoltage VDD and ground voltages of the circuit.

An identical sense amplifiers SAk are also formed for the other commondata lines IO (k) and /IO(k) shown as examples. The sources SN and SPfor the amplifying MOSFETs of these sense amplifiers SA1-SAk aresupplied in common with the above mentioned operating voltages. The knumber of sense amplifiers SA1-SAk from 1 though k start amplifyingoperation all together, and amplify the read signals read out from thecommon data lines IO and /IO corresponding to each of the senseamplifiers.

These amplified signals are output from external terminals of thesemiconductor integrated circuit device by way of output circuits notshown in the drawing. Write signals may also be supplied from theexternal terminals and supplied by way of the input circuits with noparticular restrictions. The write signals are amplified by the abovementioned sense amplifiers SA1-SAk, conveyed to the respective writedata lines by way of selected read data line and the write controlcircuits WC and written into the memory cell.

FIG. 2 is a circuit schematic showing another embodiment of the memorycircuit comprising the semiconductor integrated circuit of thisinvention. The memory charge in this embodiment is intended to benonvolatile with respect to the memory charge. The transistor forwriting nonvolatile memory charges utilizes a MOSFET with a barrierinsulator structure (hereafter simply BMOS) instead of the MOSFET usedin the previous embodiment.

In this embodiment, the N-channel MOSFET (NMOS) for the write transistorQW is instead substituted with a MOSFET (BMOS) however in all otherrespects the structure of the embodiment is the same as the firstembodiment, accordingly a description of those portions is omitted here.

FIG. 3 is a concept view of the cross sectional structure of the BMOStransistor of the embodiment. An important feature is that gateelectrodes G are formed in a vertical structure by means of gate oxidelayers (heat oxidized film thickness of tox) on both sides of the fourlayers of laminated polysilicon (poly 1 to poly 4). The gate electrodesformed on both sides of the polysilicon layers are in fact integratedinto one piece with a constant, equivalent electrical potential assubsequently related. The polysilicon 1 and polysilicon 4 are doped with10²⁰cm⁻³ of phosphorus, and form the drain D (or the source S) andsource (or drain) of the transistor. The polysilicon 2 and polysilicon 3are doped with an extremely weak concentration of phosphorus(approximately 10⁻¹⁵ to 10⁻¹⁷) forming a transistor substrate ofintrinsic polysilicon.

A tunnel layers SN1, SN2, SN3 consisting of for instance thin (2 to 3nm) silicon nitride layers are formed between the polysilicon 1 andpolysilicon 2, the polysilicon 2 and polysilicon 3, as well as thepolysilicon 3 and polysilicon 4. The tunnel layers SN1 and SN3 functionas stoppers so that the high concentration phosphorus from the drain orsource regions does not diffuse into the internal weak concentrationlayers (polysilicon 2 and polysilicon 3) when forming the transistor.

A tunnel layer that does not have a thick film is required in order tomake current flow between the source and drain. The intermediate tunnellayer SN2 restricts the off current of the transistor to a small amount.In other words, the intermediate tunnel layer SN2 functions as a stopperto prevent the positive holes or electrons emitted in the polysilicon 2and polysilicon 3 regions in the transistor from flowing as electricalcurrent between the source and drain.

When a sufficiently high positive voltage is applied to the gate, thepotential barrier of this tunnel film lowers so that a sufficientlylarge on current can flow between the source and drain. Of course, thisintermediate layer can be reduced according to the target value of offcurrent that is needed. The intermediate layer was assumed to be onelayer here, however the tunnel layer can be composed of multiple layerif required. Typical dimensions for the BMOS of FIG. 3 are, 1=0.4 μm,d=0.2 μm, and tox=10 nm. When an appropriate thickness is chosen for thetunnel layer in this type of transistor, device voltage and currentcharacteristics approaching those of a horizontal, conventional type MOStransistor with an extremely low substrate concentration can beobtained. A graph of those characteristics is shown in FIG. 4.

The maximum allowable value (I) for electrical current (IDS) flowingbetween the source and drain is found as follows, in order to assurenonvolatility for a 10 year period. When the allowable memory node (N)capacity (C) is 5fF, and the allowable memory node voltage drop (deltaV) for the 10 year period (delta t) is set to 0.1 volt, then I=C·deltaV/delta t=1.6×10⁻²⁴ A is obtained. In normal circuit design, thetransistor threshold voltage VWT is defined as a gate/source voltage(VGS) for allowing an electrical current of approximately IDS=10⁻⁸A toflow. Since the relation of IDS and VGS is linear in the current regionshown by the semi-logarithm in FIG. 4 from 10⁻²⁴A to 10⁻⁸A, increasingthe IDS by one decimal place, to set a VGS value of 100 millivolts,results in a VTW of 0.1 (volts/digit)×16(digit)=1.6 volts. Thisthreshold voltage value VTW is the minimum value for maintaining thetransistor (QW) in the off state for approximately 10 years. In theactual device design, the threshold value VTW is set to 2 volts, to takevariations in the threshold value VTW and its temperaturecharacteristics into account.

Since the maximum value of allowable current for retaining one piece ofdata of a memory cell for one day is approximately 10⁻²⁰A, then a VTW of0.1 (volts/digit)×12(digit)=1.2 volts is sufficient. The standardthreshold value VTW may be set to 1.6 volts in order to takemanufacturing variations into account. Therefore, compared tononvolatile operation, the required maximum word voltage (VDD+VTW ormore) decreases by the amount the VTW lowers so that there is less needfor a high transistor breakdown voltage for transistors inside theperipheral circuits driving the write transistors (QW) and word linesinside the memory cell.

In such cases the memory cell data is retained if a peripheral refresh(rewrite) operation for the DRAM is performed. In other words, anoperation to drive the word lines and periodically perform theaforementioned read out-rewrite in sequence on each word line will provesufficient.

FIG. 5 is a concept plan view of the memory cell for the circuit of FIG.2. The BMOS shown in FIG. 3 is utilized as the write transistor QW. Theline A-A′ of a cross section of FIG. 6 and the line B-B′ of a crosssection of FIG. 7 are respectively shown in FIG. 5. In these FIGS. 5through 7, word line (WL11) formed of a boron-doped P-channelpolysilicon layer is placed to intersect with the data line (RD1) formedof a phosphorus-doped N-channel polysilicon layer by way of a thickinsulator film. The BMOS with a cubical barrier insulator film structureshown in FIG. 3 is laminated on top of the gate electrode (N11) of aconventional MOSFET (QR of FIG. 1) so that an extremely high densitymemory cell can be obtained.

In contrast to the flat current flow in the storage MOSFET QR, the flowin the write transistor QW is clearly in a perpendicular directionrelative to the QR flow. Therefore, in contrast to the fold-over datawiring layout of the DRAM memory cell of the known art having atheoretical surface area of 8F2 (F: smallest dimension), the device ofthis invention has a surface area of 4F2 so that a cell with half thesurface area can be obtained. The coupling capacity (C) of FIG. 2, canbe formed by a heat oxidized film between the word line WL and thepolysilicon 4 as shown in FIG. 6. The size of C can be changed byadjusting the thickness of the layer of the polysilicon 4.

Compared to the DRAM cell of the known art comprised of one MOSFET andone capacitor, the memory cell of this embodiment can be manufacturedwith a smaller number of masks since the surface area of the memory cellis reduced by half and there are few irregularities on the surface.Therefore the memory chip of this invention is inexpensive and easier tobe manufactured.

The data retaining (hold) time will also be sufficiently long if thememory cell of this embodiment is set to the write transistor QWthreshold voltage (VTW) as previously described. Also, irradiation withalpha rays will make the device strongly resistant to even to soft-typeerrors. In other words, there is no pn junction in the memory cell node(N11) so that no junction leak current occurs as happens when usingMOSFETs as write transistors such as for the memory cell of FIG. 1.Also, even if electrons or positive holes are emitted internally in thecell irradiated with alpha rays, the tunnel layer will function as astopper for current flow from the positive holes or electrons so that nochange in potential occurs inside the cell. The memory cell cantherefore be operated as a nonvolatile memory.

FIG. 8 is a waveform chart for describing an example of the memorycircuit operation of FIG. 1 and FIG. 2.

The precharge signal PR is set to a high level such as VDD+VT (Here, VTis the threshold voltage of the precharge MOSFET). Also, the read datalines RD1-RDm and the write data lines WD1-WDm are precharged to a highlevel such as the power supply voltage VDD. The common data line IO, andthe common sources SP and SN for the sense amplifiers SA1-SAk areprecharged in the same way to the half-precharge voltage VDD/2.

When the precharge signal PR changes to a low level, the prechargeMOSFET sets to off, and each section such as the data lines are held atthe precharge voltage.

Hereafter, an example of writing data from the common data line pair IOin the memory cell MC11 is described. To write a high level voltage VDDor a low level voltage of 0 volts corresponding to binary information of1 or 0 in the memory node (gate) N11 of the memory cell MC11, afterapplication of a voltage VW equal or greater than VDD+VTW (VTW is thethreshold voltage of the write transistor QW) to the word line WL11, aVDD or 0 volts can be supplied to the write data line WD1, by way ofswitch MOSFET QY11 from the common data line IO, and read data line RD1and write control circuit WC1.

Here, it is important to note that when a selected voltage VDD+VTW isapplied such as to the word line WL11, the memory information of thenon-selected memory cells connected to the same word line WL11 isdestroyed. In other words, the write transistor QW for the non-selectedmemory cells MC12-MC1m connected to the word line WL11, is set to onstatus, and a precharge voltage VDD of the write data line WDm isapplied to the respective memory cell nodes N1m, etc.

In order to prevent this kind of destruction of information, the memorycell on select word line WL11 is first read out, and except for theselected memory cell MC11, the respective information that was read outis rewritten into the other non-select memory cells MC12-MC1m. Restated,data is input from the common data line IO instead of the read out data,in the rewrite operation, for the selected memory cell MC11 and the dataused as the substitute can be used for writing.

Accordingly, in the memory circuit of this embodiment, the readoperation must be performed prior to the write operation. In theembodiments in FIG. 1 and FIG. 2, the surface area of the memory cell issmall so that the word line is jointly used for reading and writing andtherefore the word line select level has two select levels consisting ofread select level VR and a write select level VW.

In non-select status, the voltages for the respective memory nodes N11,N1m of the memory cells including the binary memory information 1 and 0being read out are both lower than the MOSFET QR threshold voltage VTR.In FIG. 8, the higher voltage corresponds to 1 of the binary informationand that voltage is VN (H), so that VN (H) is assumed to be less thanVTR. Such voltage condition is realized by the capacitor C in the memorycells. In other words, when the word line WL11 has set to a non-selectlevel such as zero (0) V, a lower voltage potential for the memory nodeVN(H) is obtained by means of the coupling per the capacitor C.

The storage MOSFET QR for the plurality of memory cells MC11-MCn1connected to the one read data line RD1 is set to off status regardlessof the memory voltage VN(H) and VN (L) corresponding to the binaryinformation.

In the word line first select period, below the write transistor QWthreshold voltage, there is given a low voltage VR in which the storageMOSFET QR holding the information voltage VN (H) in the gate is at onstatus and the storage MOSFET QR holding the information voltage VN (L)in the gate is at off status, and the word line WL11 is driven by thelow voltage VR. In other words, when the word line WL11 is set to a readvoltage such as voltage VR, the voltage potential of memory node N11holding the information voltage VN (H) rises according to the selectvoltage VR by way of the capacitor C, becoming higher than the thresholdvoltage VTR and the storage MOSFET QR is set to on status, and theprecharged read data line DR1 is made to discharge.

The voltage potential of memory node N11 holding the information voltageVN (L) does not reach the threshold voltage VTR even with a rise involtage potential such as on the word line WL11 so that the storageMOSFET QR stays off and the read data line DR is maintained at theprecharge voltage.

After performing memory information read out of the memory cell to theread data line such as DR, the Y select line YS1 is set to high level(VDD+VT), and the select MOSFET QY11 is set to on status. A connectionis thus made to any or either of the read data line DR and the commondata line IO or /IO and a minute read signal VS appears by the couplingwith the respective accumulated parasitic capacitance charges.

If a read data line such as DR1 is discharged to a low level, then asmall voltage drop occurs on the common data line IO due to couplingwith the common data line IO discharged to VDD/2, and the read data lineDR1 rises by a minute voltage due to the charge supplied from the commondata line IO. Conversely, if the read data line DR1 remains precharged,then the common data line IO voltage rises by a minute amount accordingto the coupling with the common data line IO that was precharged toVDD/2, and the voltage on the read data line DR1 drops by a minuteamount, according to the charge supplied to the common data IO line.

In this way, with a binary memory information value of 1 or 0 on thecommon data line IO (or /IO) of a memory cell, the precharge voltage onthe other common data line is then set as the reference, and a minuteread out signal such as −VS or +VS appears. This read signal ±VS is setto approximately 200 to 500 millivolts when the power supply voltage VDDis about 1 to 3 volts.

This kind of differential voltage VS on the common data lines IO and /IOis amplified by the sense amplifier SA1 set to operating status inresponse to a change in the sense amplifier enabling signal SN low level(0 volts) or SP high level (VDD), and then set to a VDD high levelcorresponding to the memory information and a low level in response to aground potential of 0 volts in the circuit.

The control line WCL1 for performing line select, is set to a high levelafter verification of the voltage potential on the read data line DR1,the MOSFET QT1 comprising the write control circuit WC1 is set to onstatus and connected to the read data line DR1 and the write data lineDW1. In other words, if the voltage potential on the read data line DR1is a low level then a redistribution of the electrical charge occurswith the write data line DW1 and the voltage potential of the read dataline DR1 drops to the potential of q in the drawing. However if bothdata lines RD1 and WD1 have an equal parasitic capacitance, then theredistribution of electrical charge occurs all at once and the potentialon both data lines reaches VDD/2. Afterwards, both the data lines RD1and WD1 are set to zero (0) level by means of a discharge path formed bythe sense amplifier SA1 and the memory cell MC11. If the read data lineDR1 is at a high level, then the write data line DW1 is maintained atthe VDD corresponding to the precharge level.

In the discharge process for the data lines RD1 and WD1, when a highlevel write voltage (VDD) is added to common data line IO, both datalines RD1 and WD1 change to a high level (VDD) voltage potential inresponse to the write voltage. When a low level (0 volts) is added, bothdata lines RD1 and WD1 change to a high level (VDD) in response to thewrite voltage.

The Y select line YS1 and control line WCL1 are set to low level afterthese type of write voltages are conveyed to the write data line WD1,and the MOSFET QY11 and QT1 set to off status.

Then, in the second selection period, the word line W1 changes to a highvoltage VW to set the write transistor QW to on status. Turning thewrite transistor QW on, conveys the voltages of the write data lines WD1through WDm to the respective memory nodes N11 through N1m, writes theinformation voltages corresponding to external write signals in theselected memory cell MC11, and writes inverted voltages of the originalmemory voltages, in the other memory cells MC12 through MC1m.

When the write operations for the selected memory cells as describedabove and the so-called refresh (rewrite) operations for thenon-selected memory cell have finished, the word line WL11 is set to alow level such as zero (0) volts. The voltage such as at the memory nodeN11 of the memory cell are at a sufficiently small voltage due to thecapacitor C as previously described. Here, even when a high level suchas VDD is written in the memory node N11, after the read data line RD1has discharged to zero (0) volts, electrical current flow cannotcontinue in the storage MOSFET QR. Therefore, there is no need forproviding a circuit to set the source terminal of the storage MOSFET QRto a floating state, and as shown in the figure, a steady connection tocircuit ground potential can be achieved.

The timing for setting the MOSFET QT1 of the write control circuit WC1to an off state, or in other words, the timing for setting the controlline WCL1 to a low level non-select state is determined by the rewriteoperation of the non-select cell rather than the write operation of theselected cell.

The reason why rewrite operation is determined by the non-select cell isthat after the data lines RD1 and WD1 and RDm and WDm have reached therespective voltage potentials p, q or p′, q′ in the waveform of FIG. 8,the write data line WD1 of the select cell is driven by both the senseamplifier SA1 and the memory cell MC11, but the write data lines WD2-WDmof the non-select cells MC12-MC1m are driven only by the respectivecorresponding memory cells.

The read operation is as follows. After the read signals of the selectedmemory cells in the above write operation have been amplified and outputby the sense amplifiers SA1-SAk, there is no input of external writesignals or restated, the selected read data line RD1 and the write dataline WD1 can be kept with their voltage potential unchanged and theselect level of the word line set the high voltage VW for writing. Thecorresponding respective read voltages of selected cells andnon-selected cells for read out connected to the selected word lines arerewritten at this time.

The refresh operation is as follows. This refresh operation is mainlyapplicable when using a MOSFET as the write transistor QW such as in thememory cell shown in FIG. 1. Here, when a BMOS having a barrierinsulator structure as in the embodiment shown in FIG. 2 is used, theleakage charge from the memory node can be limited to a value smallenough to be ignored and the memory information is nonvolatile so theindividual refresh operations are unnecessary however refresh operationmay be required in some cases according to the BMOS design.

In the refresh operation, the Y select line YS in the waveform shown inFIG. 8 is not performed, and the word lines are set to voltage VR in thefirst select period in sequence from WL11 to WLln as well as WLK1 toWLkn and the read out from the memory cell is performed, signals areconveyed to the write data line by way of the write control circuit, andthen a high voltage VW can be set in the second select period and writecan be performed in the memory nodes of the memory cell.

The memory cell has an internal gain function, and if a memory cellhaving separate read and write data lines, then the circuit method ofthis embodiment can be applied unchanged in such kind of memory cell.

FIG. 9 is a circuit schematic showing another embodiment of the memorycell utilized in the memory circuit of this invention. In (A) of FIG. 9of this embodiment, a select MOSFET QR2 is formed between the read dataline RD and the drain of the storage MOSFET QR1. The gate of this selectMOSFET QR2 is connected to the word line WL. This structure may beconsidered in the memory cell of the embodiment of FIG. 1, as added withthe select MOSFET QR2 and having the capacitor C removed.

In this case, the select operation of the word line is split between theread first select period and the write and rewrite second select periodand the select voltages are changed. The select MOSFET QR2 and the writeMOSFET QW threshold voltages are set according to these select voltages.In other words, the MOSFET QR2 is at on status at read voltage VR in thefirst select period, and the write MOSFET QW is at off status. In thesecond select period, at the write voltage VW, the write MOSFET QW isset to on status. The threshold voltage of the MOSFET QR2 is set low andthe MOSFET QW threshold voltage is set high for the first select voltageVR corresponding to select/non-select operation for a word line of thiskind with a three value level; and the MOSFET QW threshold voltage isset low for the second select voltage VW.

The MOSFET QR2 has been added in this embodiment so that the number ofelements have increased however the capacitor C is not needed so thatoperation can be stabilized. In other words, the voltage margin can beincreased when accessing the memory cell.

In FIG. 9, B is a changed version of the memory cell in A of the samefigure. The word lines are separated into a write word line WWL and aread word line RWL. The gate of the write MOSFET QW is connected to thewrite word line WWL, and the gate of the select MOSFET QR2 is connectedto the read word line RWL.

In this embodiment, a select/non-select operation utilizing a 3-valuelevel for the word lines is unnecessary on account of separation of wordlines into two lines, one for read and one for write. More specifically,the read word line RWL is set to select status in the word line firstselect period, and the select MOSFET QR2 set to on status by the selectoperation of read word line RWL causes current from the memory of thestorage MOSFET QR1 (set to on or off status according to the memory cellinformation voltage) to flow in the read data line RD. If the storageMOSFET QR1 was set to on status by a high level information voltage,then the read data line RD is discharged, and if the storage MOSFET QR1was set to off status by a low level information voltage then the readdata line RD is maintained at the precharged voltage.

In the word line second select period with the write word line WWL setto select status, and the write MOSFET QW set to on status, the writevoltage conveyed to the write data line WD is written into the gate ofthe storage MOSFET QR1.

Though this embodiment increases the number of word lines by two lines,a benefit is that the write and the read word lines can respectively beset to select/non-select with binary information so that all thresholdvoltages of each MOSFET comprising a memory cell can be equivalent,thereby the design and manufacture is simplified.

In the write control circuit WC, when conveying the read signalappearing on the read data line RD unchanged to the write data line WDand performing rewrite (refresh), the memory node information voltage isinverted at that time. A data control register is then provided asdescribed next, and the control of the data input/output buffer isimplemented.

The concept for this control method utilizing as an example, a DRAMconsisting of three transistors was previously related in the known art,in ISSCC72 (International Solid-State Circuits Conference in 1972) onpp. 12-13 of the digest. In other words, a data control cell having thesame structure as a memory cell is connected to each word line. When aword line is selected, a read signal from the selected data control cellis output on the common output signal line.

The signal from the selected data control cell and the signal read outfrom the memory cell array via the sense amplifier are sent to anexclusive OR logic circuit and the output is sent as data output DO.However, the read signal to the data control register and the data inputsignal DI are summed in the same exclusive OR logic circuit and becomewrite data in the memory cell array. In order to perform datainput/output control at high speed, the channel width of the outputtransistor (equivalent to the read MOSFET QR) within the data controlcell is made larger than the channel width of the memory cell.

FIG. 10 is an essential portion of a circuit schematic showing anotherembodiment of the memory cell comprising the semiconductor integratedcircuit of this invention. In FIG. 10, one read data line RD1, writedata line WD1 and common data line IO (1) corresponding to the read dataline RD1, and one word line WL11 as well as one memory cell MC11 andwrite control circuit WC1 are used as typical elements to describeoperation.

This embodiment comprises a memory cell MC11 the same as the embodimentof FIG. 1. In this embodiment, an inverting amplifier circuit comprisedof a MOSFET QT11 and MOSFET QT12 are utilized at the write controlcircuit WC1 instead of the transfer gate MOSFET used previously. TheMOSFET QT11 is an amplifying MOSFET whose gate is connected to the readdata line RD 1. The MOSFET QT12 is an output select MOSFET for conveyingthe output from the drain of MOSFET QT11 to the write data line WD1. Thegate of the MOSFET QT12 is connected to the control line WCL1 as theline select line.

In this structure, the memory information of the memory cell MC11 isread out to the read data line RD1, the output select MOSFET QT12 is setto on status by means of the high level on the control signal WCL1, andthe inverted amplified signal obtained from the drain of the amplifierMOSFET QT11 is conveyed to the write data line WD1.

For example, if the memory node of the memory cell is stored withinformation at a high level, then as described before, the storageMOSFET QR is set to on status in the first select period of the wordline WL11, and the read data line RD1 is discharged to a low level.Since the amplifier MOSFET QT11 sets to off status upon receiving thelow level from the read data line RD1, even if the output select MOSFETQT12 is set to on status by selecting the control line WCL1, the writedata line WD1 is kept unchanged at a precharge voltage potential such asVDD. Accordingly, when the write MOSFET QW is set to on status by thesecond select period of the word line WL11, then a high level voltage,the same as the memory voltage, is written into the memory node.

Conversely, when a low level (voltage) is stored in the memory node ofthe memory cell, the storage MOSFET QR sets to off status in the firstselect period of the word line WL11 as described before, and the readdata line RD1 is maintained unchanged at a high level precharge state.Since the amplifier MOSFET QT11 sets to on status upon receiving thishigh level from the read data line RD1, when the output select MOSFETQT12 is set to on status by selecting the control line WCL1, the writedata line WD1 is discharged to zero (0) volts. Accordingly, when thewrite MOSFET QW is set to on status by the second select period of theword line WL11, then a low level voltage, the same as the memoryvoltage, is written into the memory node.

When using an inverting amplifier function in the write control circuitWC1 in this way, the previously described data control register becomesunnecessary and design of the data input/output circuits becomes simpleso that along with achieving high speed rewriting to a non-select cell,the memory cell is easier to use.

FIG. 11 is a waveform chart for describing one working example of thememory circuit operation of FIG. 10.

The word line WL11 is set to a low read voltage VR in the first selectperiod. In the non-select period, the read data line RD1 precharged to aVDD level is changed for the memory voltage of the memory node. In otherwords, in a state where an information voltage higher than the thresholdvoltage VTR of the MOSFET QR has been applied at the gate of the storageMOSFET QR, the MOSFET QR sets to on status and is discharged from VDD tozero (0) volts as shown by the solid line in the figure. In a statewhere an information voltage lower than the threshold voltage VTR of theMOSFET QR has been applied at the gate of the storage MOSFET QR, theMOSFET QR is set to off status and is maintained at the VDD prechargelevel as shown by the dotted line in the drawing.

When the Y select line YS1 is set to a high level such as VDD+VT, theread data line RD1 and the common data line IO (or /IO) are connected,and the redistribution of the electrical charge causes the read dataline RD1 and the common data line IO to set to a high level or low leveljust by the minute voltage VS based on VDD/2. Afterwards, the amplifyingoperation of the sense amplifier starts and the read data line RD1 andthe common data line IO change to a high level or a low level VDD. Whenthe control line WCL1 is set to a high level, the write data line WD1becomes a low level (zero volts) as shown by the solid line or a highlevel (VDD) as shown by the dotted line. The solid line and the dottedline in this figure correspond to changes in the voltage potential ofread data line RD1 according to the memory cell information voltages.

After the voltage potential of the write data line WD1 has been set inthis way, the voltage potential of the word line WL11 is changed to awrite high voltage VW and by setting the MOSFET QW to on status, thememory node is rewritten to a high level or a low level according to theoriginal information voltage. If the information voltage of the memorynode had dropped due to a threshold leak current from the write MOSFETQW or from a leakage current between the source, drain diffusion layersand substrate of the MOSFET QW, then the above described rewriteoperation will restore (refresh) the original information voltage.

The above described write control circuit WC, is applicable in the sameway to the memory circuit shown in FIG. 2 or the memory circuit utilizedin the memory cell shown in FIG. 9.

FIG. 12 is an essential portion of a circuit schematic showing anotherembodiment of the memory cell comprising the semiconductor integratedcircuit of this invention. In FIG. 12, one data line DL1, as well as onecommon data line IO (1) for the data line DL1, and one pair of read wordlines RWL11, write word lines WWL11, one memory cell MC11 and writecontrol circuit WC1 are used as typical elements to describe operation.

In this embodiment, the read data lines and write data lines arecomprised of the common data line DL1. In other words, the data line DL1is the read and write data line RWD.

The memory cell MC11 utilizes the same circuit as shown in FIG. 9B.However, since the read data line and the write data line jointlycomprise the data line DL1, one source and drain for the write MOSFET QWand the read select MOSFET QR2 are jointly connected to the data lineDL1. The gate of the read select MOSFET QR2 is connected to the readword line RWL11, and the gate of the write MOSFET QW is connected to thewrite word line WWL11.

The data line DL1 is connected to the common data line IO by way of thecolumn switching MOSFET QY11 comprising the data line select circuit.Though not shown in the drawing, the common data line IO is a commondata line comprising one of the previously described pair of common datalines IO and /IO.

The write control circuit WC1 of this embodiment, is comprised of MOSFETQT1, QT2 and QT3 with the same circuit configuration as the memory cellMC11. The MOSFET QT1 corresponds to the storage MOSFET QR1, the MOSFETQT2 corresponds to the read select MOSFET QR2 of the memory cell, andthe MOSFET QT3 corresponds to the write MOSFET QW. The gate of theMOSFET QT2 is connected to a first control line RCL1 for the read wordline, and the gate of the MOSFET QT3 is connected to a second controlline WCL1 for the write word line.

FIG. 13 is a waveform chart for illustrating one example of the workingexample circuit operation shown in FIG. 12. The memory circuit operationshown in FIG. 12 is described while referring to this waveform chart.

With the memory circuit in non-select status, the precharge signal PR isset to a high level such as VDD+VT, the precharge MOSFET QP sets to onstatus and the data line DL is precharged to the power supply voltageVDD.

When accessing of the memory starts, the read word line RWL11 is set toa high level such as VDD after the precharge signal PR has been set to alow level. If a high level information voltage is held in the gate ofthe storage MOSFET QR1, then the MOSFET QR1 is set to on status so thatthe data line DL as shown by the solid line in the figure, is dischargedtowards a low level (zero volts). In contrast, if a low levelinformation voltage is held in the gate of the storage MOSFET QR1, thenthe MOSFET QR1 sets to off status so that the data line DL1 remainsunchanged at a high level (VDD) as shown by the dotted line in thefigure.

The read data line and write data line are shared in this embodiment sothat when the read operation described above is finished, the read wordline RWL11 is set to low level non-select status. Afterwards, when the Yselect signal YS1 becomes a high level (VDD) by means of the data lineselect circuit, the data line DL1 and the common data line IO areconnected, and due to the dispersion of electrical charge, the commondata line IO, is changed to a low level or a high level just by theminute voltage from the VDD/2 precharge voltage as previously described.In response to this change, the voltage potential of the data line DL1changes to a potential opposite that of the common data line IO.

Though not shown in the drawing, the change in voltage potential on thecommon data line IO from the read operation, is amplified by a senseamplifier as previously described, using the precharge voltage VDD/2 ofthe other common data line /IO (not shown in the drawing) as areference, and the voltage potential of the common data line IO and theselected data line DL1 is amplified to zero (0) volts or VDD.

The control line WCL1 of the write control circuit is set to a highlevel such as VDD+VT in an operating interval including non-selectstatus. The change in voltage potential on the data line DL1 is conveyedto the MOSFET QT1, and by the change in the control line WCL1 to a lowlevel, the read out and amplified voltage on the data line DL1 is held(latched) in the gate of the MOSFET QT1. The Y select signal YS1 is alsochanged to a low level along with this latching operation, and isolatedfrom the data line DL and common data line IO (1).

During the write operation, when the Y select line YS1 is set to a highlevel, a write signal is conveyed to the common data line IO (1) by wayof the sense amplifier and input circuit, and this write signal is heldin the gate of the MOSFET QT1 of the write control circuit. In this way,in the writing operation, the write voltage from the common data line IOis latched in the write control circuit in the select memory cell, andthe read signal is latched in the write control circuit in thenon-select memory cell.

The precharge signal PR is temporarily set to a high level, and the dataline DL1 is precharged to the VDD level. After this precharging isfinished, the control line RCL1 and the write word line WWL11 are set toa high level. The select level for the write word line WWL11 is set as ahigh voltage such as VDD+VTW.

If a high level was latched at the gate of MOSFET QT1 of the writecontrol circuit WC1, then the MOSFET QT1 is at on status so the dataline DL1 is discharged to a low level by way of the MOSFET QT2, and thislow level is written into the gate of the MOSFET QR1. However, if a lowlevel was latched at the gate of MOSFET QT1 of the write control circuitWC1, then the MOSFET QT1 is at off status so the data line DL1 remainsunchanged at a high level, and this level is written into the gate ofthe MOSFET QR1.

An operation of this type, allows the same write/read and refreshoperations as in the circuit embodiments of FIG. 1 and FIG. 2 to beperformed utilizing one data line. The number of data lines in thisembodiment can be halved so that a simplified circuit can be achieved.

In the above kind of select cell read operation or non-select cellre-write operation, in the write control circuit, a re-inverted voltageis input to the memory node of the memory cell so that there is noinversion of a voltage to a high level/low level each time a memory nodevoltage is read out from the memory cell. Therefore, a data controlregister as previously related, becomes unnecessary and the memory cellis easier to use.

When a BMOS device having a barrier insulator structure as in theembodiment of FIG. 2, is used instead of a MOSFET as the writetransistor of the memory cell and a vertical structure is used for theBMOS device, not only can the surface area of the memory cell be reducedbut the memory (information) voltage can also be made nonvolatile. Byalso using a BMOS device for the MOSFET QT3 constituting the writecontrol circuit, the surface area of the control circuit can also bereduced just the same as for the memory cell.

FIG. 14 is an essential portion of a circuit schematic showing anotherembodiment of the memory cell comprising the semiconductor integratedcircuit of this invention. When the memory capacity becomes large, thenumber of memory cells connected to read data lines and write data linesbecome numerous and as a result, parasitic capacitance increases andsuch increase delays operation.

In this embodiment, the read data lines and write data lines areseparated vertically, (top and bottom) to reduce the parasiticcapacitance in the data lines. In other words, line connection isperformed selectively centering around the write control circuit WC andprecharge circuit and data line select circuit by way of the selectionswitches QRCU, QWCU and, QRCL, QWCL.

In this structure, the data line select circuit and write controlcircuit WC can be jointly used with respect to the vertically separateddata lines RDU, WDU and RDL, WDL. Any memory cell of the previouslydescribed embodiments shown in FIG. 1, FIG. 2 and FIG. 9 correspondingto the read data line and write data line may be used as the memory cellMC. A circuit as shown in FIG. 1 or a circuit with an invertingamplifier function as shown in FIG. 10 may be utilized as the writecontrol circuit.

By setting the respective select signals SU and SL in FIG. 14respectively to a high voltage such as VDD+VT, the vertically separatedtwo pairs of data lines can be simultaneously precharged to VDD level bythe precharge MOSFET QP1 and QP2.

After the precharging operation is complete, by setting the selectsignal SL corresponding to the data line for selection (for example RDL,WDL) unchanged at a high level, and setting the select signal SUcorresponding to a non-select data line (RDU, WDU) to a low level, theMOSFET QRCU and QWCU can be set to an off state, and isolated from thewrite control circuit WC and data line select circuit. On the selectside, with the write control circuit and data line select circuitconnected to the data lines RSL and WDL, read, write or refreshoperations can be performed as previously described. In this embodiment,separating the data lines reduces the data line length by half, and theparasitic capacitance and parasitic resistance is reduced so that highspeed operation is possible.

The above embodiments incorporate a method for precharging the read dataline to VDD in order to identify read signals from memory cells havinginternal gain.

FIG. 15 is an essential portion of a circuit schematic showing yetanother embodiment of the memory cell comprising the semiconductorintegrated circuit of this invention. When the memory cell comprisesread data lines and write data lines and has a memory cell gainfunction, both of these read and write data lines are set tocomplementary levels when the write control circuit operates. In otherwords, when the signal read out from the read data line is a low level,the write data line is set to an opposite or high level. In thisembodiment, this point is noted and a CMOS latch circuit is formed inthe write control circuit and the embodiment is contrived for high speedsignal changes in the data line.

Since greater semiconductor integration has resulted in utilization ofmemory cells comprising small elements and since many memory cells maybe connected to one data line RD, the parasitic capacitance increasesand a comparatively long time is required to discharge the read dataline RD down to a full level of zero (0) volts.

This embodiment takes advantage of the fact that the write data line WDis set to a fixed voltage potential during read out and by using thisfixed voltage potential as a reference voltage, at the point where aminute voltage differential occurs with the read data line RD, thevoltage potential of the read data line RD can be set by amplificationperformed by sense amplifier comprised of CMOS latches with high drivepower, and the voltage potential of the write data line WD for thenon-select cell can also be set at the same time.

The sense amplifier utilizes a CMOS latch circuit comprised of a CMOSinverter circuit consisting of the N-channel MOSFET QN1, QN2 andP-channel MOSFET QP1, QP2 and their respective cross-connected inputsand outputs. This CMOS latch circuit is supplied with an enablingvoltage SP such as the power supply voltage VDD during triggering of thesources of P-channel MOSFET QP1, QP2, and amplification is performedwhen an enabling voltage SN such as zero (0) volts is applied duringtriggering of the source of the N-channel MOSFET QN1, QN2.

In order to acquire the read signal, the write data line WD isprecharged with an intermediate voltage of VDD/2 as the prechargevoltage. The read data line RD on the other hand, is supplied with ahigh voltage VDD/2+δ added with just a minute voltage δ as the prechargevoltage.

There are no particular restrictions on this structure and the read dataline RD and write data line WD are connected to the pair ofcomplementary common data lines IO and /IO by way of a data line selectcircuit comprised of a column switching MOSFET QY1 and QY2. The commondata lines IO and /IO are precharged to VDD/2 the same as above.

When a sense amplifier is formed in the data lines RD and WD in thisway, utilizing the common data lines IO and /IO as low amplitude signallines, the read signal can be amplified by the main amplifier. Ofcourse, a sense amplifier comprised of a CMOS latch circuit as relatedabove can also be used.

In the write operation, a polarized differential voltage correspondingto the write information from the common data lines IO and /IO issupplied to the sense amplifier of the selected data lines RD and WD,and amplified to a high level/low level binary voltage by the applicablesense amplifier. In this structure, the sense amplifier functioning asthe write control circuit performs inversion amplification so that thepreviously mentioned data control register is not necessary, and thestructure is easy to use. The signal amplitude of the data lines RD andWD can be reduced by half to a high level/low level such as centering onVDD/2 so that low current consumption can also be achieved.

As shown in the waveform chart of FIG. 16, in order to achieve the abovedescribed read operation, the precharge voltage VDD/2 for the write dataline WD must be set to a voltage higher by an amount δ in order toobtain a precharge voltage of VDD/2+δ on the read data line RD. Thereason for setting a voltage differential is that, when both RD and WDare precharged to the same voltage potential of VDD/2, and a low levelis held in the memory node of the memory cell, when no discharge path isformed such as during read out, the voltage potential of the read dataline RD stays precharged to VDD/2, and is equal to the voltage potentialon the write data line WD functioning as the reference voltage so thatthe sense amplifier is disabled.

By providing a voltage differential by a minute voltage δ in theprecharge voltage as shown above, a discharge path is formed by thememory cell read operation as shown in waveform (A), so that the voltagepotential on the data line RD changes to low level. When the relativevoltage potential has reversed, amplifying operation is performed bysetting the timing signals SP and SN of the source to on for enablingthe sense amplifier, to make the data lines RD and WD change to highlevel/low level at high speed.

As shown in waveform (B), when a discharge path is not formed by thememory cell read operation, the data line RD is maintained at a highlevel just by the voltage potential δ and by setting the timing signalsSP and SN to on to enable the sense amplifier, and by performingamplifying operation, the data lines RD and WD are made to changebetween high level/low level at high speed.

The effects of this invention as obtained from the above embodiments areas follows.

First, by utilizing a memory cell containing a write transistor and astorage MOSFET to retain information voltage in the gate, a word lineplaced to intersect with a write data line conveying write data and aread data line conveying a read signal corresponding to the on or offstatus of the memory cell storage MOSFET, and a memory cell array forconnecting to the control terminal of the write transistor of the memorycell and for issuing an output on the read data line corresponding tothe read signal from the memory cell in response to a select signal fromthe write transistor, and by means of a data line select circuit toselect one read data line from among the plurality of read data linesand connect to either a first or second common data line, and prechargethe read data line to a first voltage within a non-select period, and ina first select period, by selecting a word line for reading anddischarging the word line to a second voltage by means of a storageMOSFET of the memory cell set to on status, by precharging the first andsecond common data lines to a third voltage between the first and secondvoltages in the non-select period, and in the first select period, theread signal appearing on one common data line corresponding to thecharge dispersion with the read data line selected by the data lineselect circuit is amplified using the precharge voltage of the othercommon data line as the reference voltage, and after conveying the writesignals to the write data line in the second select period if needed, bysetting the word line to a high voltage, setting the write transistor toon status and by writing or rewriting in the memory cell, there can beachieving the effect that the memory cell itself has an amplifyingfunction, and read out of information is nonvolatile so that a memorycircuit can be attained having a simplified circuit design that is easyto use.

Second, by having approximately the same number of read data linesconnected by way of the data line select circuit to the first and secondcommon data lines, and read signals are formed in one of the common datalines by electrical charge dispersion, and a sense amplifier is formedcomprising a differential amplifier circuit utilizing the prechargevoltage of the other common data line as the reference voltage so thatin addition to the above effects of the invention, stable and high speedread operation can be achieved.

Third, by utilizing a complementary metal-oxide semiconductor latchcircuit consisting of a pair of CMOS inverter circuits havingcross-connected inputs and outputs as the differential amplifiercircuit, along with obtaining high speed read out as related above, aneffect is rendered that the write operation onto the selected memorycell can be performed at high speed.

Fourth, by providing a write control circuit to convey signals from theread data line, between the read and write data lines, to the write dataline, in addition to the above effects of the invention, an effect isrendered that rewriting can be easily performed when the memory voltagehas dropped due to a leakage current or other factors.

Fifth, by utilizing a read data line, a write data line and a transfergate MOSFET connecting these read and write data lines as the writecontrol circuit, in addition to the above effects of the invention, aneffect is rendered that the circuit is simplified.

Sixth, by utilizing an inverting amplifier circuit to invert and amplifythe signal voltages of the read data lines, and convey the signalvoltages to the write data lines as the write control circuit, inaddition to the above effects of the invention, an effect is renderedthat the data control register can be omitted and the circuit becomeseasier to use.

Seventh, by forming a structure with a barrier insulator film configuredin a cubic shape having an electrical current path in a verticaldirection towards the surface of the gate electrode on a MOSFET, as thewrite transistor comprising the memory cell, and by forming a capacitorbetween the word line and the gate of that MOSFET, in addition to theabove effects of the invention, an effect is rendered that a largedecrease in the cell surface area and nonvolatile memory voltage can beobtained or an increase in data holding time can be achieved.

Eighth, by utilizing a MOSFET as the write transistors comprising thememory cell, and by forming a capacitor between the word line and thegate of that MOSFET holding the information (memory) voltage, inaddition to the above effects of the invention, an effect is renderedthat the memory circuit can be formed without the addition of anyspecial manufacturing process.

Ninth, by separating the word line into write word lines and read wordlines, setting the read word line to select status in a first selectperiod, and setting the write word line to select status in a secondselect period, by connecting that write word line to the gate of aMOSFET functioning as the write transistor of the memory cell, and byconnecting the gate of the select MOSFET in serial to the read word linefor the storage MOSFET gate holding the memory voltage, the select levelof the word line can be set to a binary (two value) level so that inaddition to the above effects of the invention, an effect is renderedthat the word line select operation is simplified and the operatingmargin is expanded.

Tenth, by making the write word line and the read word line a commonword line, and setting the write MOSFET threshold value higher than theselect MOSFET threshold value, and by setting only the select MOSFET toon status in the first select period, and by also setting the writeMOSFET to on status in the second select period, so that the aboverelated memory operations are achieved and an effect is rendered thatthe memory circuit can be formed without the addition of any specialmanufacturing process.

Eleventh, by making the read data line and the write data line into onecommon data line, forming a dummy cell with the same circuit as thememory cell to function as the write control circuit, the read signal orthe write signal from the data line is written into the write controlcircuit, and is conveyed as a write signal to the common data line forthat read out signal, and by writing this write signal into the memorycell selected by the word line, in addition to the above effects of theinvention, an effect is rendered that the circuit is simplified and thememory operation does not require a data control register.

Twelfth, by utilizing a MOSFET as the write transistor comprising thememory cell, and connecting the write word line to the gate of thatMOSFET, and forming a select MOSFET between the data line and storageMOSFET whose gate holds the memory voltage of the memory cell,connecting the read word line to the gate of that MOSFET, and connectingthe read control line corresponding to the read word line utilizing thewrite control circuit consisting of the dummy cell to the write controlline corresponding to the write word line, the write control circuit canthen be controlled by enabling the write control line and read controlline, so that in addition to the above effects, an effect is obtainedthat the circuit is simplified and the memory operation does not requirea data control register.

Thirteenth, by selectively connecting the write data line and read dataline by means of a switching circuit mainly for the write controlcircuit, precharge circuit and data select circuit, in addition to theabove effects, parasitic capacitance in the data line and parasiticresistance can be reduced so that high speed and stable operation can beachieved.

Fourteenth, by utilizing a memory cell containing a write transistor anda storage MOSFET to retain information voltage in the gate, a word lineplaced to intersect with a write data line conveying write signal and aread data line conveying a read signal corresponding to the on or offstatus of the memory cell storage MOSFET, and a memory cell array forconnecting to the control terminal of the write transistor of the memorycell and for issuing an output on the read data line corresponding tothe read signal from the memory cell in response to a select signal fromthe write transistor, by forming a sense amplifier comprised of a CMOSlatch circuit formed between the read data line and the write data line,precharging the read data line to a first voltage potential in a firstperiod, precharging the write data line to a second voltage smaller thanthe first voltage in the first period, selecting the word line in thesecond period and discharging the read data line to a third voltagepotential by the on status of a storage MOSFET of the memory cell, andafter the read data line has been set to a first voltage or a thirdvoltage according to the memory information voltage of the memory cell,the sense amplifier is set to operating status and amplification to ahigh level or low level is performed according to the operation voltageof the sense amplifier, and by means of a data line select circuit, byselecting one pair from among the plurality of write data linescorresponding to read data lines and connecting to a first and secondcommon data line, high speed and stable operation can be achieved.

Fifteenth, by setting the power supply voltage and the circuit groundvoltage potential as the high and low level corresponding to the senseamplifier operation voltages, setting the second voltage to one-half ofthe power supply voltage, and setting the first voltage to a minimumvoltage higher than the second voltage required for stable amplifyingoperation, an effect is rendered that the amplitude on the data linebecomes smaller and a circuit with high speed operation and low powerconsumption can be achieved.

A basic explanation was related above based on the embodiments of theinvention rendered by the inventors, however needless to say, the scopeof this invention is not limited by the above description andencompasses a variety of changes within the spirit and range of theinvention. In FIG. 1 and FIG. 2 for example, a positive voltage was usedfor VDD, however a P-channel MOSFET may be substituted for the N-channelMOSFET as a precharge MOSFET. By using a P-channel MOSFET, the controlsignal PR having a low level such as the circuit ground potential willreach an active level so that a high voltage larger than VDD is notrequired. Therefore, even when the memory circuit was in non-selectstatus for a long time, when utilizing an N-channel MOSFET, there is noneed for special measures such as continual operation of a charge pumpcircuit to maintain the precharge signal at a boosted voltage.

In the memory cells of FIG. 9 and FIG. 12, the write transistor QW maybesubstituted with a MOSFET with a barrier insulator structure (or BMOS)and formed as a vertical structure on the gate of the storage MOSFETQR1. In other words, this MOSFET with a barrier insulator structure, canbe utilized as a write transistor in all the memory cells shown in theseembodiments as well as in dummy cells used as a write control circuit orall of the memory cells as the data control resistor. Nonvolatile memoryvoltage can in principle be achieved by utilizing this MOSFET withbarrier insulator structure. A large decrease in the surface area of thecircuit cell can also be achieved.

The differential amplifier circuit formed in the common data line IO and/IO may use an operational amplifier circuit as the differentialamplifier circuit other than the CMOS latch circuit as mentioned in theembodiments.

The memory array structure may also utilize a hierarchical structure ofthe known art, placing a plurality of memory arrays in the direction ofthe word line, and grouping the word lines into main word lines andsub-word lines such as in a dynamic RAM. The memory circuit, along withusing digital circuits for digital processing such as with amicroprocessor CPU, may be internally stored inside one semiconductorintegrated circuit device, itself comprising a general purpose memorycircuit. An input circuit is formed in the general purpose memorycircuit to input address signals and control signals. In a memorycircuit internally incorporated in a digital circuit, the applicableinput circuits are omitted, and address signals and control signals aresupplied by way of an internal bus to the decoder.

INDUSTRIAL APPLICABILITY

This invention is widely applicable to semiconductor integrated circuitdevices consisting of a memory cell comprising a storage MOSFETcombining memory operation and amplifying operation, and a writetransistor to write information voltages in the gate of the storageMOSFET, or to semiconductor integrated circuit devices incorporatingmemory circuits and other logic circuits.

What is claimed is:
 1. A semiconductor integrated circuit devicecomprising: a memory array, wherein said memory array further includes:a plurality of memory cells, each having a storage MOSFET holding aninformation voltage in a gate of the storage MOSFET and set to an ON orOFF state according to the information voltage, and a write transistorsupplying a write information voltage to the gate of the storage MOSFET;a plurality of write data lines, each being applied with the writeinformation voltage given as the information voltage of correspondingones of the memory cells; a plurality of read data lines, each beingapplied with read signals corresponding to the ON or OFF state of thestorage MOSFET of the memory cells; a word line structure connected tothe control terminals of the write transistors of the memory cells; adata line select circuit selecting one of the plurality of read datalines; and a first and a second common data line being connected to oneof the read data lines selected by the data line select circuit,wherein, during a non-select state, the word line structure is set to afirst voltage to set the storage MOSFET to OFF state regardless of theinformation voltage, wherein, in a first select period, the writetransistor is set to OFF state, the word line structure is set to asecond voltage which makes the storage MOSFET to ON state to dischargethe read data line when the information voltage is high level or to OFFstate when the information voltage is low level so that the read dataline is not discharged, wherein, in a second select period, in whicheither the information voltage to be written into the write data linesor the signal voltage corresponding to the read signal are applied, theword line structure is set to the second voltage which makes the writetransistor to ON state, wherein the first and second common data linesare precharged to a precharge voltage that is an intermediate voltagebetween a high level voltage and a low level voltage at a time ofamplifying voltages on the first and the second common data lines in thenon-select state, and wherein the read signal which appears on one ofthe first and second common data lines corresponding to a charge sharewith the read data line selected by the data line select circuit isamplified using the precharge voltage of the other of the first andsecond common data lines as a reference voltage.
 2. A semiconductorintegrated circuit device according to claim 1, wherein the same numberof read data lines are respectively connected by way of the data lineselect circuit to each of the first and second common data lines, andwherein the semiconductor integrated circuit device includes adifferential amplifier circuit that amplifies the read signal producedon one of the first and second common data lines by the charge share,using the precharge voltage of the other of the first and second commondata lines as the reference voltage.
 3. A semiconductor integratedcircuit device according to claim 2, wherein the differential amplifiercircuit includes a CMOS latch circuit having a pair of CMOS invertercircuits, the pair of CMOS inverter circuits having cross-coupled inputsand outputs, and an operating voltage of the CMOS latch circuit issupplied during amplification.
 4. A semiconductor integrated circuitdevice according to claim 3, further comprising: a write control circuitconnected between the read data lines and the write data lines, whereinthe write control circuit applies a signal on the read data lines to thewrite data lines.
 5. A semiconductor integrated circuit device accordingto claim 4, wherein the write control circuit is comprised of a transfergate MOSFET connecting the read data lines with the write data lines. 6.A semiconductor integrated circuit device according to claim 4, whereinthe write control circuit is an inverting amplifier circuit to invertand amplify the signal voltage from the read data lines and to applyinverted amplified signals to the write data lines.
 7. A semiconductorintegrated circuit device according to claim 4, wherein each of thewrite data line and the read data line is divided into two data lines,wherein the write control circuit, a precharge circuit, and the dataline select circuit are connected with one of the write data line andthe read data line being divided into the two data lines via a firstswitch circuit, and wherein the write control circuit, the prechargecircuit and the data line select circuit are connected with the other ofthe write data line and the read data line being divided into the twodata lines via a second switch circuit.
 8. A semiconductor integratedcircuit device according to claim 1, wherein the write transistorincluded in the memory cells is a MOSFET produced in a three-dimensionalshape so as to have an electrical current path in a vertical directionrelative to the main surface of the semiconductor substrate on which thesemiconductor integrated circuit device is produced.
 9. A semiconductorintegrated circuit device according to claim 8, wherein each of theplurality of memory cells further includes a capacitor between the wordline structure and the gate of the MOSFET.
 10. A semiconductorintegrated circuit device according to claim 8, wherein the writetransistor is a MOSFET with a barrier insulator structure.
 11. Asemiconductor integrated circuit device according to claim 1, whereinthe write transistor included in the memory cells comprises a MOSFET,and wherein each of the plurality of memory cells further includes acapacitor between the word line structure and the gate of the storageMOSFET that holds the information voltage in the gate.
 12. Asemiconductor integrated circuit device according to claim 1, whereinthe word line structure comprises a write word line structure and a readword line structure, and the read word line structure is set to selectstate in the first select period, and the write word line structure isset to select state in the second select period, wherein the writetransistor of the memory cells comprises a MOSFET, and a gate of theMOSFET is connected to the write word line structure, wherein a gate ofthe storage MOSFET holds the information voltage, and the storage MOSFETis connected to a select MOSFET serially, and wherein a gate of theselect MOSFET is connected to the read word line structure.
 13. Asemiconductor integrated circuit device according to claim 12, whereineach of the write data line and the read data line is divided into twodata lines, wherein the write control circuit, a precharge circuit, andthe data line select circuit are connected with one of the write dataline and the read data line being divided into the two data lines via afirst switch circuit, and wherein the write control circuit, theprecharge circuit and the data line select circuit are connected withthe other of the write data line and the read data line being dividedinto the two data lines via a second switch circuit.
 14. A semiconductorintegrated circuit device according to claim 1, wherein each of theplurality of the memory cells further includes a select MOSFET having asource-drain path inserted between a drain of the storage MOSFET and theread data line, wherein a gate of the select MOSFET is connected to theword line structure, wherein the write transistor is a MOSFET, andwherein a threshold voltage of the write transistor is set higher than athreshold voltage of the select MOSFET, and in the first select periodof the word line structure is set to a first voltage in which only theselect MOSFET is set to ON state, and in the second select period theword line structure is set to a second voltage in which the writetransistor is also set to ON state.
 15. A semiconductor integratedcircuit device according to claim 1, wherein the read data line andwrite data line are comprised of one common data line, wherein the onecommon data line is connected to a dummy cell, having the same circuitas the memory cells, as a write control circuit, wherein the read signalfrom the common data line or the write signal applied to the common dataline are written into the write control circuit, and wherein the readsignal from the dummy cell is applied to the corresponding common dataline as the write signal, and is written into the memory cell selectedby the word line structure.
 16. A semiconductor integrated circuitdevice according to claim 15, wherein the word line structure includes awrite word line structure and a read word line structure, wherein thewrite transistor included in the memory cells comprises a MOSFET,wherein a gate of the MOSFET is connected to the write word linestructure, wherein each of the plurality of memory cells and the dummycell further include a select MOSFET having a source-drain path insertedbetween a drain of the storage MOSFET and the one common data line,wherein a gate of the select MOSFET is connected with the read word linestructure, wherein the write control circuit having the dummy cell isconnected to a read control line corresponding to the read word linestructure, and connected to a write control line corresponding to thewrite word line structure, and wherein the operation of the writecontrol circuit is controlled by enabling the write control line andread control line.
 17. A semiconductor integrated circuit devicecomprising: a plurality of memory cells, each having a write transistorto supply a write information voltage to a gate of a storage MOSFET, thestorage MOSFET holding an information voltage in the gate and being madeto ON or OFF state in response to the information voltage; a pluralityof write data lines transferring write information voltage applied tothe plurality of memory cells; a plurality of read data linestransferring read signals corresponding to the ON or OFF state of thestorage MOSFET in the plurality of memory cells; a word line structureconnected to control terminals of the write transistor in the pluralityof memory cells and outputting the read signal to the read data linefrom the memory cells in response to a select signal from the writetransistor; a data line select circuit selecting one pair from aplurality of pairs comprised of the read data lines and thecorresponding write data lines; a first and second common data linerespectively connected to one pair of the plural pairs of read datalines and write data lines by way of the data line select circuit; and asense amplifier having a CMOS latch circuit provided between the readdata line and the write data line, wherein the read data line isprecharged to a first voltage in a first period, and the write data lineis precharged to a second voltage smaller than the first voltage in thefirst period, wherein the word line structure is selected and isdischarged to a third voltage by the ON state of the storage MOSFET in asecond period, wherein, after the read data line has been set to thefirst voltage or the third voltage corresponding to the informationvoltage of the memory cells, the sense amplifier is set to an operatingstate and a high level or low level are set according to the operationvoltage of the sense amplifier.
 18. A semiconductor integrated circuitdevice according to claim 17, wherein the high level and the low levelcorresponding to the operation voltage of the sense amplifier correspondto the power supply voltage and the circuit ground voltage potential,respectively, wherein the second voltage is set to one-half of the powersupply voltage, and wherein the first voltage is set to a voltage higherthan the second voltage by the minimum voltage required for stableamplifying operation of the sense amplifier.